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Implement all instructions (except sync and system call) in the RV32I instruction set based on Lab3 using RISC-V 64-bit ISA. RISC-V basically supports unaligned memory addressing. The file that implemented this is dmem_unaligned.sv, so please refer to it. Also, the instruction stored in instruction memory is supposed to verify only some commands, so you need to modify them to make all commands verifiable. In this task, in the single-processor design implementation Verilator is used to implement design modules implemented using SystemVerilog. Verilator runs on Linux OS by default, so you must install Linux on the WSL of your personal PC. After performing the task, you must submit image files that capture source files, compilation sсrіpts, and waveform. I also attach the code I wrote. I need to make sure it′s implemented properly, and a debugging process.

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